I designed my first ASIC in 1981. It had 400 gates and was part of a large mainframe computer. At the time, this was state-of-the-art. Since then, ASIC density has grown by more than five orders of magnitude.

After designing a lot of hardware, I became interested in the process of design itself. It seemed to me that we kept stumbling across the same problems and inefficiencies time and time again. I began to see that improving the development process was a more challenging problem than design itself. I became interested in verification as I saw it as the most challenging problem.

One day, around 1990, I read an article in EE Times describing a new way of verifying hardware called formal verification. The article promised that all you would have to do is give your design to the tool and it would tell you what all the bugs are. Well, I thought this was the most exciting in the world and, so, I started studying it. I learned enough to be dangerous, but quickly realized that I had a different perspective than all other experts in the area because of my hardware background. I had my own ideas and decided to pursue them, eventually leading to a Ph.D. in formal verification. I then went on to found an EDA company, Nusym Technology, Inc., based on these ideas.

For a long time, I have wanted to find a forum to present what I have learned about designing complex hardware/software systems. I hope this will be informative and I welcome any discussion, especially as I think some of what I will say will be controversial.